Substrate-design tools are known that operate in the environment of design of systems and electronic circuits, namely, EDA (Electronic Design Automation) environments. In particular, among EDA environments there is known, for example, the Cadence design suite, which comprises, in a version thereof, a platform, referred to as “Virtuoso Platform”, for full-custom design of integrated circuits, which comprises entry of the schematics, behavioral modeling (Verilog-AMS), circuit simulation, full-custom layout, steps of verification at the physical level, extraction of netlists. The aforesaid platform envisages some indications for analyzing the substrate contacts of the transistors, for example, in the QRC Extraction Cadence module for calculation of the parasitic effects in the chip.
The assisted electronic-design tools available hence provide a very limited support when the interactions are to be assessed between electronic devices of the above electronic systems and circuits in a chip at the level of the substrate of the chip itself.